The present invention relates generally to memory arbitration schemes, and more particularly to a method and apparatus of arbitrating requests to a memory having more than one bank.
In response to consumer demand for high performance computer systems, manufacturers are developing computer systems that utilize multiple processors, instead of a single processor. The theory behind multi-processor systems is that if a one processor system provides a certain level of performance, then a two processor system could provide twice the performance of the one processor system, and a three processor system could provide three times the performance of the one processor system, etc. While in theory this may be true, the reality is that, due to various limiting factors, each additional processor that is added to a computer system only increases the performance by a fraction. As a result, a particular two processor system may only provide 1.5 times the performance of a one processor system.
One such performance limiting factor is that, these multi-processor systems typically have a common or shared memory resource in which the processors store and retrieve instructions and data. In these systems, the processors typically access the shared memory by issuing, upon a processor bus, memory requests to a memory controller. The memory controller decodes the request and then satisfies the request by controlling the transfer of information (instructions or data) between the processor and the shared memory in accordance with the type of request. However, since these multi-processor systems are typically designed such that only a single request may access the shared memory at a given time, an arbitration scheme must be implemented which grants a single request access to the shared memory.
Since these processors do not have exclusive use of the memory, at times a first processor must wait for a second processor's request to complete before the first processor's request can be satisfied. This performance limiting factor of waiting for another processor's request to complete is even further aggravated by the fact that due to physical characteristics of the shared memory certain memory accesses take longer than others. Since in the typical case, a memory controller has more than one memory request from which to select a request to process, a memory controller, which makes an informed decision as to which memory request to select, can increase the performance of the multi-processor system by reducing the amount of time that the processors, as a whole, are waiting for requests.
What is needed therefore, is a method and apparatus of arbitrating requests to a multi-banked memory which increases the performance of a computer system by reducing the amount of time that the processors, as a whole, wait for memory requests to be completed.